1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to complex circuits formed according to silicon-on-insulator (SOI) architecture on the basis of semiconductor alloys, such as silicon/germanium, for enhancing transistor performance.
2. Description of the Related Art
Complex integrated circuits include a large number of transistors, such as P-channel and N-channel field effect transistors, when a CMOS device is considered. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect renders the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates great efforts for the adaptation and possibly the new development of process techniques, it has been proposed to also enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length. One efficient technique is based on the concept of modifying the lattice structure in the channel region, for instance by creating tensile or compressive strain, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region may increase the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Therefore, in some approaches, for instance, a silicon/germanium layer is provided in or below the channel region to create tensile or compressive strain therein. In other strategies, a silicon/germanium material is formed in the drain and source regions in the form of a strained layer, thereby inducing a respective strain in the adjacent channel region. The silicon/germanium alloy may be formed on the basis of epitaxial growth techniques, wherein the respective process parameters may be controlled so as to incorporate a specified amount of germanium into the silicon, which substantially determines the degree of lattice mismatch that may finally be obtained in the respective channel region.
Moreover, with respect to transistor performance, in addition to other advantages, the SOI architecture has been continuously gaining in importance for manufacturing MOS transistors, due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, a relatively thin crystalline silicon layer is formed on a buried insulation layer and the drain and source regions are formed within the thin silicon layer. Thus, the semiconductor portion, in which the drain and source regions as well as the channel region are formed, may be dielectrically encapsulated by the buried insulating layer and respective trench isolations, which provide the lateral insulation to neighboring devices. Due to these advantages, the strain engineering is also used in SOI transistor devices, in which the silicon/germanium material may be grown on the basis of the thin upper silicon layer in order to obtain the desired strain characteristics in the respective channel region, thereby significantly contributing to a performance gain of SOI transistors.
Thus, when using strain engineering on the basis of silicon/germanium alloys as described above, it is important to calibrate the epitaxial growth process and also to monitor the process result in order to maintain product reliability and uniformity. For this purpose, well-established techniques may be used, one of which includes x-ray diffraction techniques, in which the response of the crystalline structure of a dedicated portion on a semiconductor device with respect to an incoming x-ray beam is evaluated in order to determine, for instance, the germanium contents of the epitaxial material. Although corresponding techniques may work well for bulk devices, problems may arise for SOI devices, as will be explained with reference to FIGS. 1a-1c in more detail.
FIG. 1a schematically illustrates a typical test arrangement for determining the contents of germanium in a silicon/germanium layer epitaxially grown on a bulk substrate. A substrate 100 comprises a crystalline base material 101, for example a silicon substrate, on which is formed an epitaxial silicon/germanium layer 102, which may be formed as a strained semiconductor material, when the layer 102 has substantially the same lattice spacing as the crystalline base material 101. In other cases, a significant portion of the layer 102 may represent a relaxed silicon/germanium layer, when, for instance, a corresponding buffer layer (not shown) may be provided between the base material 101 and the layer 102 in order to continuously increase the amount of germanium, thereby also continuously increasing the corresponding lattice spacing, which may finally substantially correspond to the natural lattice spacing of silicon/germanium, which, as previously explained, may depend on the amount of germanium incorporated in the silicon-based material. Furthermore, the layer 102 may be formed on the basis of any well-established epitaxial growth techniques, wherein respective process parameters may also have an influence on the characteristics of the final layer 102.
In order to determine the respective germanium contents of the layer 102, an x-ray diffraction system 150 may be used, which may comprise a radiation source 151 that is configured to provide a substantially mono-energetic x-ray beam 153, which may interact with the device 100. Furthermore, an x-ray detector 152 is provided to receive a scattered x-ray beam 154, wherein the angular relationship between the source 151, the detector 152 and the substrate 101 may be varied so as to detect respective intensity variations depending on the respective set of crystallographic planes responding to the incoming x-ray beam 153. A corresponding measurement result illustrating the intensity variation in relation to the angle of incidence is schematically illustrated on the right-hand side of FIG. 1a, wherein a corresponding curve may also be referred to as a Rocking curve.
It should be appreciated that the x-ray beam 153 has a large penetration depth and thus interacts simultaneously with the layer 102 and also with the base material 101 such that the corresponding intensity spectrum may exhibit the response of a significant portion of the irradiated area of the substrate 100. For instance, an appropriate scan area for the angular range for the angle of incidence may be selected for an appropriately selected wavelength of the beam 153, which may be accomplished on the basis of the well-known Bragg relation. For instance, the intensity curve as shown in FIG. 1a may schematically illustrate a respective response for the reflection of (004) crystal planes on the basis of a wavelength of the incident beam 153 of 1.54 Å, corresponding to the copper Kα line. Due to the significant amount of silicon material in the base layer 101, a prominent peak may be obtained during the angular scan, as is indicated in the spectrum, while a corresponding peak, which is significantly reduced in intensity and may have an increased width compared to the silicon peak, may be obtained for the silicon/germanium layer 102, due to the slightly different lattice spacing and thus a different Bragg angle. Based on the angular difference between the two peaks, the contents of germanium in the layer 102 may be calculated and may therefore be used for calibrating and/or evaluating the corresponding epitaxial growth process. Consequently, for bulk substrates having formed thereon an epitaxially grown silicon/germanium layer, a highly efficient process control may be accomplished on the basis of the respective measurement data.
FIG. 1b schematically illustrates the corresponding situation for an SOI substrate 100, which may comprise the base material 101, a buried insulating layer 103, for instance a silicon dioxide layer, and a silicon layer 104 formed on the buried insulating layer 103. The substrate 100 of FIG. 1b, when subjected to the x-ray diffractrometric measurement, may also produce a response that is a combination of the layers 103 and 101, wherein the buried insulating layer 103 may only add substantially diffused radiation, thereby contributing to the overall noise of the measurement. The right-hand side of FIG. 1b schematically illustrates a respective response, wherein the peaks of the layer 101 and 104 may exhibit a certain angular difference, depending on the relative crystalline orientation of the layers 104 and 101. For instance, when the substrate 100 is formed by wafer bond techniques, a slight mismatch, for instance a twist and/or a tilt of the respective crystallographic orientations, may be caused, since crystals of different crystalline substrates are combined. Thus, as indicated by the arrows 101D and 104D, a tilt between respective crystallographic planes may result in a corresponding different location (in the angular scan range) of the respective intensity peaks, wherein, as previously explained with the layer 102 in FIG. 1a, the significantly reduced thickness of the material of the layer 104 with respect to the base material 101, of which a significant portion may contribute to the overall response to the incoming x-ray beam, may result in the significantly reduced intensity. Depending on the resolution of the measurement system 150, and depending on the degree of lattice mismatch, the corresponding peak of the layer 104 may be resolved or may not be unambiguously determined.
FIG. 1c schematically illustrates the situation when the substrate 100 represents an SOI substrate, whose SOI silicon layer 104 may receive the silicon/germanium alloy 102 so that a patterned structure is formed, which may additionally comprise any non-crystalline areas 105, such as dielectric materials and the like. For instance, the silicon/germanium alloy 102 may be formed as a substantially embedded material that may be grown in respective recesses formed in specific layer portions of the SOI silicon layer 104. In this case, the response of the residue of the SOI layer 104 may be even further reduced, similarly to the response of the material 102, while nevertheless a respective peak of the base material 101 is provided with high intensity due to the high amount of material contributing to the response of the incoming x-ray. The right-hand side of FIG. 1c may schematically illustrate a corresponding response, wherein a recognizable peak for the material 102 may still be obtained, while the respective peak of the silicon layer 104 may no longer be detectable due to the significant background noise. Consequently, in conventional measurement strategies for determining the contents of germanium in patterned SOI substrates on the basis of x-ray diffractrometry, the prominent peak of the base material 101 is used for the calculation. As previously explained, however, the corresponding crystalline orientation of the base material 101 may have a specific deviation with respect to the layer 104, while the characteristics of the alloy material 102 are determined by the layer 104 so that the corresponding calculation may provide a highly inaccurate result, which may reduce the performance of a corresponding process to calibrate and/or monitor the respective epitaxial growth process.
In view of the situation described above, there exists a need for determining characteristics of a semiconductor alloy on the basis of x-ray diffractrometry while avoiding or at least reducing the effects of one or more of the problems identified above.